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A reconfigurable analog VLSI neural network architecture with non‐linear synapses

Identifieur interne : 002822 ( Main/Exploration ); précédent : 002821; suivant : 002823

A reconfigurable analog VLSI neural network architecture with non‐linear synapses

Auteurs : G. M. Bo [Italie] ; D. D. Caviglia [Italie] ; M. Valle [Italie] ; R. Stratta [Italie] ; E. Trucco [Italie]

Source :

RBID : ISTEX:0E10E6ED535E6CF674BF18ACA0C86D4D13F475B3

English descriptors

Abstract

In this paper a reconfigurable analog VLSI neural network architecture is presented. The analog architecture implements a Multi‐Layer Perceptron whose topology can be programmed without any modification of the off‐chip connections. The architecture is scaleable and modular since it is based on a single‐chip configurable basic module. To obtain a robust behaviour with respect to noise and errors introduced in the computation by analog circuits, we use non‐linear synapses and linear neurons as neural primitives. © 1998 John Wiley & Sons, Ltd.

Url:
DOI: 10.1002/(SICI)1097-007X(199805/06)26:3<307::AID-CTA14>3.0.CO;2-5


Affiliations:


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