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Scheduling of OR-parallel Prolog on a scalable, reconfigurable, distributed-memory multiprocessor

Identifieur interne : 000051 ( Istex/Corpus ); précédent : 000050; suivant : 000052

Scheduling of OR-parallel Prolog on a scalable, reconfigurable, distributed-memory multiprocessor

Auteurs : J. Briat ; M. Favre ; C. Geyer ; J. Chassin De Kergommeaux

Source :

RBID : ISTEX:21A37369D25D3F96C68D9EF3B8122264041C5ED6

Abstract

Abstract: The OPERA project aims at efficiently implementing Prolog on a scalable, reconfigurable distributed-memory architecture. The OPERA computational model exploits OR-parallelism following a classical multisequential approach: each processor executes a complete Prolog engine based on the WAM; inter-processor communication is reduced to work installation, the complete state of an active Prolog engine being copied to an idle one. Scheduling is performed by a hierarchy of specialized processors, operating in parallel of the computation of the Prolog program. To avoid costly synchronization, schedulers use an approximate representation of the state of the system. Because of the important overhead of task installation in a distributed-memory system, only workers having a large amount of work to execute can give work to idle workers. Several dynamic work regulation strategies have been designed and are currently being tested. The prototype implementation of OPERA on a transputer-based Supernode is one of the most efficient existing Prolog implementations on the transputer and reaches effective speed-ups in parallel over efficient sequential Prolog systems.

Url:
DOI: 10.1007/3-540-54152-7_76

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ISTEX:21A37369D25D3F96C68D9EF3B8122264041C5ED6

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<Para>The OPERA project aims at efficiently implementing Prolog on a scalable, reconfigurable distributed-memory architecture. The OPERA computational model exploits OR-parallelism following a classical multisequential approach: each processor executes a complete Prolog engine based on the WAM; inter-processor communication is reduced to work installation, the complete state of an active Prolog engine being copied to an idle one. Scheduling is performed by a hierarchy of specialized processors, operating in parallel of the computation of the Prolog program. To avoid costly synchronization, schedulers use an approximate representation of the state of the system. Because of the important overhead of task installation in a distributed-memory system, only workers having a large amount of work to execute can give work to idle workers. Several dynamic work regulation strategies have been designed and are currently being tested. The prototype implementation of OPERA on a transputer-based Supernode is one of the most efficient existing Prolog implementations on the transputer and reaches effective speed-ups in parallel over efficient sequential Prolog systems.</Para>
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<abstract lang="en">Abstract: The OPERA project aims at efficiently implementing Prolog on a scalable, reconfigurable distributed-memory architecture. The OPERA computational model exploits OR-parallelism following a classical multisequential approach: each processor executes a complete Prolog engine based on the WAM; inter-processor communication is reduced to work installation, the complete state of an active Prolog engine being copied to an idle one. Scheduling is performed by a hierarchy of specialized processors, operating in parallel of the computation of the Prolog program. To avoid costly synchronization, schedulers use an approximate representation of the state of the system. Because of the important overhead of task installation in a distributed-memory system, only workers having a large amount of work to execute can give work to idle workers. Several dynamic work regulation strategies have been designed and are currently being tested. The prototype implementation of OPERA on a transputer-based Supernode is one of the most efficient existing Prolog implementations on the transputer and reaches effective speed-ups in parallel over efficient sequential Prolog systems.</abstract>
<note>This work has been partially sponsored by the Centre National d'Etude des Télécommunications (CNET) and ESPRIT project P1085.</note>
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